Design Verification Internship
- Posted
- Date not provided
- Last verified at source
- 8 days ago
Design Verification Internship
Edveon Technologies is inviting applications from 2027 graduating engineering students currently pursuing their qualifying degree at colleges/institutions located in Tamil Nadu, who are interested in building a career in the Semiconductor and VLSI industry, with a focus on Design Verification (DV).
disciplines with:
● Strong logical thinking and problem-solving ability
● Interest in programming and technology
● Genuine interest in VLSI and semiconductor engineering
● Willingness to learn and work on challenging engineering problems
● Minimum 60% aggregate in 10th, 12th/Diploma and Undergraduate degreePrior VLSI training is not mandatory.
1. Logical & Aptitude Test
Eligible candidates will attend a Logical Reasoning and Aptitude Test conducted at various examination centres across Tamil Nadu.
2. Merit-Based Shortlisting
Candidates who clear the aptitude test will be shortlisted for the next stage based on merit and the overall selection criteria.
Academic performance in 10th, 12th/Diploma and Undergraduate studies will also be considered as part of the selection process.
3. 1-to-1 Technical Interview
Shortlisted candidates will attend a one-to-one technical interview to assess their technical fundamentals, logical thinking, problem-solving ability and interest in VLSI/Design Verification.
4. Internship Selection
Candidates who successfully complete the selection process will be considered for the paid internship program.
Selected candidates will undergo structured training, hands-on learning and industry exposure focused on VLSI Design Verification.
The program will provide exposure to:
1. Specification Reading
2. Feature Analysis
3. Verification Planning
4. Development & Coding
5. Simulation & Testing
6. Debugging
7. Coverage Closure
INTERNSHIP TO FULL-TIME OPPORTUNITY
Up to 75 paid internship opportunities are planned for the 2027 graduating batch.
Based on performance, learning progress and job requirements, selected candidates may be considered for full-time employment with Edveon Technologies after successful completion of the internship program.
● Practical Design Verification exposure
● Mentoring from experienced engineers
● Problem-solving and debugging experience
● Exposure to semiconductor engineering practices
● Potential pathway to full-time employment
Please provide accurate academic and personal information in this form. Eligibility and selection will be determined based on the criteria and selection process defined by Edveon Technologies.
Location:
Siruseri, Chennai
Eligibility:
2027 Graduating Batch
Job Description:
VLSI Design Verification Internship Up to 75 Paid Internship Opportunities for 2027 GraduatesEdveon Technologies is inviting applications from 2027 graduating engineering students currently pursuing their qualifying degree at colleges/institutions located in Tamil Nadu, who are interested in building a career in the Semiconductor and VLSI industry, with a focus on Design Verification (DV).
Important: The 2026 Graduate Hiring Drive Is Now Closed.
This opportunity is exclusively for the 2027 graduating batch.Eligibility:
Students pursuing engineering in ECE, EEE, VLSI, Electronics and related engineeringdisciplines with:
● Strong logical thinking and problem-solving ability
● Interest in programming and technology
● Genuine interest in VLSI and semiconductor engineering
● Willingness to learn and work on challenging engineering problems
● Minimum 60% aggregate in 10th, 12th/Diploma and Undergraduate degreePrior VLSI training is not mandatory.
Internship Selection Process
The selection process will consist of multiple stages:1. Logical & Aptitude Test
Eligible candidates will attend a Logical Reasoning and Aptitude Test conducted at various examination centres across Tamil Nadu.
2. Merit-Based Shortlisting
Candidates who clear the aptitude test will be shortlisted for the next stage based on merit and the overall selection criteria.
Academic performance in 10th, 12th/Diploma and Undergraduate studies will also be considered as part of the selection process.
3. 1-to-1 Technical Interview
Shortlisted candidates will attend a one-to-one technical interview to assess their technical fundamentals, logical thinking, problem-solving ability and interest in VLSI/Design Verification.
4. Internship Selection
Candidates who successfully complete the selection process will be considered for the paid internship program.
Program Timeline:
January 2027 – June 2027Selected candidates will undergo structured training, hands-on learning and industry exposure focused on VLSI Design Verification.
The program will provide exposure to:
1. Specification Reading
2. Feature Analysis
3. Verification Planning
4. Development & Coding
5. Simulation & Testing
6. Debugging
7. Coverage Closure
INTERNSHIP TO FULL-TIME OPPORTUNITY
Up to 75 paid internship opportunities are planned for the 2027 graduating batch.
Based on performance, learning progress and job requirements, selected candidates may be considered for full-time employment with Edveon Technologies after successful completion of the internship program.
What Edveon Offers:
● Industry-oriented learning● Practical Design Verification exposure
● Mentoring from experienced engineers
● Problem-solving and debugging experience
● Exposure to semiconductor engineering practices
● Potential pathway to full-time employment
Who Should Apply?
If you are a 2027 engineering graduate currently studying at a college/institution located in Tamil Nadu and are genuinely interested in starting your career in VLSI and semiconductor engineering, you are encouraged to apply.Please provide accurate academic and personal information in this form. Eligibility and selection will be determined based on the criteria and selection process defined by Edveon Technologies.