Design Verification Trainee

Job Description:

Edveon is hiring Design Verification Trainees who want to build a career in the semiconductor industry. Prior VLSI or Design Verification experience is not required — a strong foundation in aptitude, logical thinking, and engineering fundamentals matters more. Prior exposure to VLSI is a plus, but not mandatory.

Key Responsibilities:

● Strong aptitude and problem-solving ability● Logical and analytical thinking● Good understanding of Digital Electronics● Programming fundamentals in any one language (C, C++, Java, or Python)● Ability to grasp and apply technical concepts logically● Curiosity and genuine interest in VLSI and semiconductor technology● Willingness to learn, take ownership, and persist through technical problems

Required Qualifications:

● B.E. / B.Tech in ECE, EEE, CSE, IT, or AI & DS
● M.E. / M.Tech in VLSI, Embedded Systems, or Power Electronics● Engineering candidates only

Graduation Year:

● 2023, 2024, and 2025 passouts only

Training:

Selected candidates undergo structured training — delivered via EdvLearn and Edveon's engineering team — covering:

● Digital Design & Verification
● SystemVerilog (including Verification and Testbench Development)
● UVM Basics
● Analog Basics

What Edveon Offers:

● Structured, industry-oriented training with monthly stipend
● Practical exposure to Design Verification● Assessment-based full-time employment
● Meals and transport facilities
● A career path in semiconductor Design Verification

Selection Process:

Application → Eligibility Screening → Written Test → Technical Assessment & Interview → Structured Training → Assessment → Full-Time Employment for Selected Candidates

Written test covers: Aptitude/Logical Reasoning, Digital Electronics, and Programming

Please note:

● No direct walk-ins
● Candidates interviewed by Edveon Technologies within the past 3 months are not eligible for this drive