Deep-tech Work India
KeenSemi

Verification Engineer

Noida, Bangalore and Hyderabad · 2 to 3 Years

Semiconductor Design VerilogSystemVerilogVHDLVerificationFPGA
Posted
Date not provided
Last verified at source
2 days ago
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Role : Perform verification using UVM and SVM on IP, Blocks and top. _Desired Skills:_ * Ability to understand RTL quickly * familiar with ASIC/FPGA verification methodology * able to create a Verilog/VHDL module test specification from the ASIC/FPGA functional specification * should have the Knowledge of the System Verilog’s Universal Verification Methodology (UVM) Experience : 2 to 3 Years