Senior FPGA Engineer

• Location: Hyderabad
• Employment: Full Time

Job Description

We are seeking a RTL/FPGA Design Engineer to design, develop, and validate FPGA-based digital hardware for satellite sub-systems. The role involves end-to-end ownership of FPGA development from system and micro-architecture through RTL implementation, verification, hardware bring-up, and on-board validation working closely with system, hardware, PCB, and embedded software teams to deliver reliable, high-performance designs for space environments.

Key Responsibilities

• Contribute to system, DSP, and board-level architecture for satellite sub-systems
• Partition algorithms across FPGA hardware and embedded software
• Design and develop RTL using VHDL / Verilog for datapaths, control logic, and interfaces
• Create micro-architecture specifications, block diagrams, and design documentation
• Perform functional simulation, timing analysis, and timing closure
• Synthesize and implement designs using Xilinx Vivado and integrate Xilinx IP cores
• Support board-level bring-up, debugging, and lab validation using JTAG, logic analyzers, and oscilloscopes
• Collaborate with PCB, systems, and embedded teams on interfaces, pinout, and constraints
• Support subsystem integration and troubleshooting at test facilities
• Prepare and maintain SRS, test plans, ATPs, validation and compliance documentation
• Participate in design reviews and readiness reviews following aerospace-quality processes

Qualifications

• B.E./B.Tech in Electronics & Communication / Electrical / VLSI (or equivalent)
• 8 years of hands-on experience in RTL and FPGA design
• Technical Skills (Must-Have)
• Strong experience in Verilog RTL design (working knowledge VHDL)
• Hands-on with Xilinx FPGA toolchain (Vivado) – synthesis, P&R, constraints, timing closure
• Functional and timing simulation; testbench development
• Board-level debugging and lab validation experience
• Interfaces: PCIe, Ethernet, UART, SPI, I²C
• Familiarity with DDR / LPDDR memory interfaces and AXI protocols
• Version control using Git / SVN

Tools & Technologies

• HDLs: VHDL, Verilog (SystemVerilog / SystemC – plus)
• FPGA Tools: Xilinx Vivado; timing and simulation tools
• Lab Tools: JTAG, logic analyzer, oscilloscope
• Modeling: MATLAB / Octave
• Version Control: Git (SVN acceptable)

Nice-to-Have/Domain Skills

• Experience with satellite, aerospace, defence, or safety-critical systems
• DSP implementation on FPGA (FFT, FIR, fixed-point optimization)
• Knowledge of fault-tolerant and radiation-mitigation techniques (ECC, SEU, TMR)
• Strong documentation and cross-functional communication skills