Role : Manage 2 -3 hierarchical blocks, DFT simulations, debug , pattern generation. Support scan chain insertion and post silicon debug
_Desired Skills:_
* DFT logic integration and verification using testmax / tessent / modus
* Experience on improving coverage.
* Gate Level DFT verification with and without timing using vcs / ncsim.
* Pattern generation, verification and delivery to ATE team.
* Post silicon debug and support on failing patterns.
* Good experience on EDA tools of reputed vendor like Mentor, Synopsis.
* LBIST experience is a plus.
* DFT mode STA and timing closure support is a plus
Experience : 2 to 3 Years
Deep-tech Work India