Vicharak Date not provided
Surat, Gujarat · Full Time
Semiconductor Design CadenceSynopsysAnalog Design
Vicharak Date not provided
Surat, Gujarat
VLSISemiconductor Design PythonDFTPhysical Design
Vicharak Date not provided
Surat, Gujarat
Semiconductor Design PythonShell ScriptingDFT
Vicharak Date not provided
Surat, Gujarat
Semiconductor Design PythonShell ScriptingDFT
Edveon Technologies Date not provided
Chennai / USA
VLSI VerilogSystemVerilogRTL Design
Tonbo Imaging Date not provided
FPGA PythonSystemVerilogCAN/LIN
Moschip 19 Jun 2026
Physical Design · Hyderabad · Full Time
Semiconductor Design RTL DesignPhysical DesignCadence
Moschip 19 Jun 2026
Physical Design · Bangalore, Hyderabad · Part Time
Semiconductor Design RTL DesignPhysical DesignCadence
Moschip 18 Jun 2026
Physical Design · Hyderabad, Bangalore · Full Time
Semiconductor Design Physical DesignCadenceSynopsys
Tessolve 17 May 2026
Digital · Sarjapur Road, Bengaluru, Karnataka, India · Regular Employee - Probation
Backend EngineeringFrontend EngineeringEmbedded Systems Physical DesignCadenceSynopsys
Tessolve 17 May 2026
Digital · Sarjapur Road, Bengaluru, Karnataka, India · Regular Employee - Probation
Backend EngineeringFrontend EngineeringEmbedded Systems Physical DesignCadenceSynopsys
Tessolve 14 May 2026
Digital · Noida, Noida, Uttar Pradesh, India, Electronic City, Bengaluru, Karnataka, India, Guindy, Chennai, Tamil Nadu, India, Jubilee Hills, Hyderabad, Telangana, India, ORR, Bengaluru, Karnataka, India, Whitefield, Bengaluru, Karnataka, India · Regular Employee - Probation
Backend EngineeringFrontend EngineeringEmbedded Systems PythonSystemVerilogCAN/LIN
Tessolve 14 May 2026
Digital · Electronic City, Bengaluru, Karnataka, India, Whitefield, Bengaluru, Karnataka, India, Jubilee Hills, Hyderabad, Telangana, India · Regular Employee - Confirmed
Backend EngineeringFrontend EngineeringEmbedded Systems PythonSystemVerilogCAN/LIN
Tessolve 13 May 2026
Digital · Noida, Noida, Uttar Pradesh, India, Electronic City, Bengaluru, Karnataka, India, Jubilee Hills, Hyderabad, Telangana, India, ORR, Bengaluru, Karnataka, India · Regular Employee - Probation
Backend EngineeringFrontend EngineeringEmbedded Systems PythonSystemVerilogCAN/LIN
Tessolve 11 May 2026
Digital · Electronic City, Bengaluru, Karnataka, India · Regular Employee - Confirmed
Semiconductor DesignElectrical Engineering PythonSystemVerilogVerification
Tessolve 11 May 2026
Digital · Sarjapur Road, Bengaluru, Karnataka, India · Regular Employee - Confirmed
Backend EngineeringFrontend EngineeringEmbedded Systems PythonPhysical DesignCadence
Moschip 13 Jan 2026
SES · Bangalore, Hyderabad · Full Time
VLSI CC++Verilog
Moschip 8 Jan 2026
SES · Bangalore, Hyderabad · Full Time
VLSI CC++Verilog
Moschip 8 Jan 2026
SES · Bangalore, Hyderabad · Full Time
VLSI CC++Verilog
Tessolve 11 Dec 2025
Analog · Hubli, Hubli, Karnataka, India · Regular Employee - Confirmed
Semiconductor Design PythonCadenceSynopsys
Tessolve 7 Dec 2025
Digital · Sarjapur Road, Bengaluru, Karnataka, India · Regular Employee - Probation
Semiconductor Design RTL DesignDFTPhysical Design
UNMANND 30 Aug 2025
Bengaluru, Karnataka · Full time
VLSI CC++Verilog
Tessolve 27 May 2024
Test Engineering (TSI_TE_TE) · Electronic City, Bengaluru, Karnataka, India · Regular Employee - Confirmed
Data ScienceSemiconductor Design PythonShell ScriptingDFT
LeadIC Design Date not provided
Engineering · Hyderabad / Bengaluru · Full Time
Semiconductor Design PythonVerilogSystemVerilog
KeenSemi Date not provided
Noida, Bangalore and Hyderabad
Semiconductor Design DFTPhysical DesignSynopsys
KeenSemi Date not provided
Noida, Bangalore and Hyderabad
Semiconductor Design CAN/LINPhysical DesignSynopsys
KeenSemi Date not provided
Noida, Bangalore and Hyderabad
Semiconductor Design DFTPhysical DesignSynopsys
KeenSemi Date not provided
Noida, Bangalore and Hyderabad
Semiconductor Design CadenceSynopsysLow Power Design
KeenSemi Date not provided
Noida, Bangalore and Hyderabad
VLSI PythonVerilogRTL Design
Innosilica Date not provided
Bangalore, Hyderabad, Noida
Semiconductor Design Physical DesignSynopsysDFM / DFMA
