Role : Take up ownership of blocks independently (RTL2GDSII)
_Desired Skills:_
* Interaction with RTL designers on timing paths.
* Functional and DFT constraint development exposure.
* Based on PPA targets, should be able to implement different floorplans.
* Come up with strategies to control congestion through understanding of specific block level challenges.
* Should be able to built the clock tree on multi-clocks, synchronous and asynchronous clock domain partitions.
* Should be good in timing analysis.
* Ability to own DRC/LVS/ANTENNA clean ups at block level.
* Implementation experience on IR/EM analysis and fixes.
* Should be good in innovus/icc2, tempus/primetime & genus/design compiler
* Have low power implementation experience & should be good in scripting.
Experience : 2 to 3 Years
Deep-tech Work India