Role : Manage hierarchical blocks and pattern retargetting to top level, simulations debug and can think of different ways to improve coverage, scan insertion and post silicon bringup.
_Desired Skills:_
* Good experience in scan insertion and ATPG in block level and pattern retargetting in top level.
* DFT logic integration and verification using testmax / tessent / modus
* Experience on improving coverage and can support with innovative ways to improve coverage.
* Gate Level DFT verification with and without timing using vcs / ncsim.
* Pattern generation, verification and delivery to ATE team.
* Post silicon debug and support on failing patterns.
* Good experience on EDA tools of reputed vendor like Mentor, Synopsis.
* JTAG and MBIST/LBIST insertion and pattern generation.
* Can manage and resolves scan issues, DRCs for small teams.
Experience : 4 to 6 Years
Deep-tech Work India