Sr. DFT Engineer

On-site. Surat. Gujarat

• Defect modeling and test methodology development for advanced process nodes, advanced packaging technologies
• Perform top/block-level DFT insertion including scan compression, boundary scan, 1500 wrapper, ATPG and pattern simulation
• Verify DFT circuitry and interface with other blocks, debug timing simulation issues
• Closely work with physical design team to resolve timing constraints/issues
• Be able to quickly understand problem statements and innovate solutions for DFT, diagnosis and yield learning
• Work independently and own the task from DFT specification to final pattern delivery

• BTech and above in Relevant Engineering Courses
• 2 + years of hands-on experience with DFT and test flow with commercial EDA tools
• Experience in RTL and Gates verification and simulation.
• Strong fundamental knowledge of DFT techniques include JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. , MBIST and LBIST
• Experience with Vendor DFT Complier’s, Tetramax and VCS is, Tessent and Modus/Encounter is required.
• Strong programming skills in Python/TCL and shell scripting is required