_Desired Skills:_
* Hands-on experience with focus on front-end complex RTL design involving logic IP design.
* Efficient in Coding in Verilog
* Creating testbenches in Verilog or UVM
* Running simulations using ncsim, vcs or similar tools
* Debugging design issues using waveform viewers
* Creating SDC and UPF constraints for synthesis.
* Understanding timing reports.
* Must be familiar with all stages of the ASIC design flow (including specification, architecture, and design implementation)
* Highly motivated and skillful at solving difficult technical problems
* Experience with scripting in Perl/Python/Shell
Experience : 2 to 4 Years
Deep-tech Work India